Memory elements (also called arrays) in integrated circuits are tested by a special test engine, which is sometimes called an array built in self test (ABIST) engine. The ABIST engine is used to apply design-specific test patterns that are generated by a state machine. The purpose of the test patterns is to detect any fail mechanism in the array that is due to the characteristics of the storage element (or cell), such as the physical and/or functional specifics of the cell. The ABIST engine may communicate with the array under test by providing, for example, address, data, and control signals to the array. This communication therefore requires a test interface. Because this interface is considered overhead from a functional point of view, the impact of the interface in terms of area, performance, and power should preferably be minimized.
In existing integrated circuit (IC) designs, the ABIST address, data, and control signals may be multiplexed (MUXed) with the functional address, data, and control signals. This is accomplished, for example, by adding a MUX stage between the functional signals and the ABIST signals. However, a drawback of this arrangement is that the MUX stage, and specifically the corresponding propagation delay, is in the functional path. The position of the MUX stage impacts the cycle time and, thereby, the operating frequency of the array. A further drawback is that a MUX stage is required for each individual address, data, and control bit, which results in the consumption of chip real estate and additional power.
Alternatively, in existing IC designs, the ABIST engine may be interfaced to the array via the logic scan ring. Again, this interface may be controlled by a MUX stage that is placed at the beginning of the scan chain. Because these scan rings are not timing critical, adding a MUX stage has no significant impact on the cycle time or operating frequency. However, a major drawback of this arrangement is that the test data from the ABIST engine needs to be scanned into the latches, which may take many cycles (e.g. a number of cycles equal to the number of latches) and, therefore, may result in excessive test times. Furthermore, for specific cycle-to-cycle tests, such as those where two different addresses are read into two consecutive clock cycles, two or more sets of data must be loaded. As a result, duplication of these latches is required, thus affecting area and power.
Therefore, a need exists for new approaches to interfacing the ABIST engine to memory elements under test in order to optimize chip performance, minimize the amount of chip real estate needed, minimize the amount of power consumption, and minimize test time.